Time-to-market pressure, design complexity and cost of ownership for masks are driving the industry towards on-silicon re-programmable solutions for a larger class of designs than ever before, for achieving fast products’ derivatives implementation, manage product inventory, adapt to standards without carrying the costs for new set of masks. Within this trend, Dataquest have estimated that the ASIC/ASSP market with embedded programmable logic cores will pass $3 Billion by 2005.

“FlexEOS innovative architecture has been designed for full and fast re-programmability, high density, optimized silicon area, low consumption, high speed” said Frederic Reblewski, M2000 President and co-founder. “Optimized hardware architecture is as important as an efficient and flexible software implementation flow for both the integration of the macro on silicon, as well as for the customization in the specific application environment. Once the FlexEOS macro has been implemented in the ASSP chip, it’s possible to dynamically implement different function using software tools only”
“We offer a re-programmable hard macro with the flexibility and easy-to-use of a soft macro”, continued Frederic Reblewski.

About FleXEOS embedded re-programmable core
M2000’ FleXEOS IP family includes a series of re-programmable logic blocks, SRAM based with different sizes and portable to various silicon technologies.
M2000 FleXEOS’ architecture is organized as a hierarchical multi-level interconnect .An array of logic elements called Multi Function logic Cell (MFC) allows implementation of digital logic. The MFC is a 4 input /1 output programmable structure associating a 4 inputs Look-Up Table and a storage element.
A typical core comprising 3,000 MFC elements, offering to the user an equivalent ASIC gate capacity of 30,000 gates (200K FPGA equivalent gates), has a size of 8 mm2 on the ST HCMOS8 0.18 micron technology. It’s maximum measured frequency is 340MHz for typical system clock of 150MHz, with very low power consumption: standby current less than 100µA and a power consumption measured at 100mW when running 120 counters at 66MHz.
Availability
The FleXEOS macro has been silicon proven on ST HCMOS8, 0.18 micron technology and requires standard CMOS logic process only.

About M2000
M2000 S.A.R.L was created in 1996 by 3 EDA (Electronic Design Automation) veterans, all founders of Meta Systems, which Mentor Graphics acquired in May 1996. At Meta Systems, they developed SIMEXPRESS, the first emulation system based on custom FPGAs (Field Programmable Gate Array.) The three founders hold numerous patents in the field of configurable logic and its applications for electronic system testing. M2000’s goal is to design and develop state of the art configurable logic technology targeted at the rapidly growing SoC (System on a Chip) market. Corporate headquarters are located at 4, rue René Razel, 91400 SACLAY, France -+ 33 1 69 35 32 50 - World Wide Web site: www.m2000.fr
Email: info@m2000.fr

ST, STM, HCMOS is a registered trademark of ST Microelectronics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.



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